1. Field of the Invention
The present invention relates to a liquid crystal display device. More particularly, it relates to a color filter on thin film transistor (COT) type in-plane switching (IPS) mode liquid crystal display (LCD) device and a method of fabricating the same.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices are being developed as the next generation of display devices because of their characteristics of light weight, thin profile, and low power consumption. In general, an LCD device is a non-emissive display device that displays images by making use of a refractive index difference through utilizing optical anisotropic properties of liquid crystal molecules interposed between an array substrate and a color filter substrate. When an electric field is applied to liquid crystal molecules, the liquid crystal molecules are reoriented. As a result, light transmittance of the liquid crystal molecules is changed according to an alignment direction of the reoriented liquid crystal molecules.
The LCD device includes two substrates disposed to have their respective electrodes face each other, and a liquid crystal layer is formed between the respective electrodes. When a voltage is applied to the electrodes, an electric field is generated between the electrodes to modulate light transmittance of the liquid crystal layer by reorienting liquid crystal molecules, thereby displaying images.
FIG. 1 is an exploded perspective view of a liquid crystal display device according to the related art. In FIG. 1, a liquid crystal display (LCD) device 11 includes an upper substrate 5, a lower substrate 22 and a liquid crystal layer 14 interposed between the upper and lower substrates 5 and 22. A black matrix 6 is formed on the upper substrate 5 and a color filter layer 8 including sub-color filters is formed on the black matrix 6. A common electrode 18 is formed on the color filter layer 8. A pixel electrode 17 and a thin film transistor (TFT) “T” as a switching element are formed on the lower substrate 22 in a pixel region “P.” The pixel electrode 17 is formed of a transparent conductive material, such as indium-tin-oxide (ITO) and indium-zinc-oxide (IZO). The pixel region “P” is defined by a gate line 13 and a data line 15. The TFT “T” is connected to the gate line 13 and the data line 15. In addition, a storage capacitor “CST”, which is connected in parallel with the pixel electrode 17, is formed on the gate line 13. A portion of the gate line 13 is used as a first electrode of the storage capacitor “CST” and a metal pattern 30 having an island shape, which is in the same layer and is formed of the same material as the source and drain electrodes of the TFT “T,” is used as a second electrode of the storage capacitor “CST.” Since the metal pattern 30 is connected to the pixel electrode 17, the same signal that is applied to the metal pattern 30 is also applied to the pixel electrode 17.
The upper substrate 5 and the lower substrate 22 can be referred to as a color filter substrate and an array substrate, respectively. Since the LCD device 11 is obtained by attaching the upper substrate 5 having the color filter layer 8 and the lower substrate 22 having array elements, such as the gate line 13, the data line 15 and the TFT “T,” the performance of the LCD device 11 may deteriorate due to light leakage resulting from an alignment error.
FIG. 2 is a schematic cross-sectional view taken along a line “II—II” of FIG. 1. In FIG. 2, an upper substrate 5 and a lower substrate 22 are spaced apart from each other, and a liquid crystal layer 14 is interposed between the upper substrate 5 and the lower substrate 22. A thin film transistor (TFT) “T” including a gate electrode 32, an active layer 34, a source electrode 36 and a drain electrode 38 is formed on the lower substrate 22 and a passivation layer 40 is formed on the TFT “T.” A pixel electrode 17 connected to the drain electrode 38 of the TFT “T” is formed in a pixel region “P” defined by a gate line 13 and a data line 15. A storage capacitor “CST” that is connected in parallel to the pixel electrode 17 is formed over the gate line 13.
A black matrix 6 corresponding to the gate line 13, the data line 15 and the TFT “T” is formed on the upper substrate 5. A color filter layer 8 is formed on the black matrix 6 to correspond to the pixel region “P.” The data line 15 is separated by a first distance “IIIa” from the pixel electrode 17 to prevent vertical cross talk. In addition, the gate line 13 is also separated from the pixel electrode 17 by a second distance “IIIb.” Since light leaks through a first gap between the data line 15 and the pixel electrode 17 and a second gap between the gate line 13 and the pixel electrode 17, the black matrix 6 of the upper substrate 5 covers the first and second gaps. Moreover, the black matrix 6 covers the TFT “T” to prevent incidence of light onto the active layer 34 through the passivation layer 40.
Since a misalignment may occur during an attachment process of the upper and lower substrates 5 and 22, the black matrix 6 is designed with a misalignment margin. Accordingly, aperture ratio is reduced due the misalignment margin that is included in the black matrix. Moreover, since a misalignment exceeding the misalignment margin causes a light leakage at the first and second gaps, display quality deteriorates.